Si-LSI semiconductor devices, particularly Si-MOSFETs, are becoming more and more sophisticated year after year, as the LSI technology is advancing. In recent years, however, the limits of the lithography technology have been pointed out from the viewpoint of the process technology, while the limits of carrier mobility have been pointed out from the viewpoint of device physics. In this trend, it is becoming more difficult to manufacture more sophisticated Si-LSI semiconductor devices.
Recently, attention has been paid to a method of applying a “strain” to the active layer to form a device, as a method for improving electron mobility, which is one of the indicators of improvements in performance of Si-MOSFETs. When a strain is applied to the active layer, the band structure of the active layer changes, and carrier scattering in the channel is restrained. Accordingly, the mobility of the carriers (electrons and holes) is enhanced. Specifically, a mixed crystal layer made of a material having a larger lattice constant than that of Si, or a strain-relaxed SiGe mixed crystal layer (hereinafter referred to simply as the SiGe layer) having a Ge concentration of 20%, for example, is formed on a Si substrate, and a Si layer is formed on the SiGe layer. The strain derived from the difference in lattice constant is applied to the Si layer, and the Si layer turned into a strained Si layer. It was reported that, when such a strained Si layer was used as the channel, the electron mobility was greatly enhanced and became approximately 1.76 times higher than that in a case where a non-strained Si layer was used as the channel.
Also, as a method of forming a strained Si layer on a Semiconductor On Insulator (SOI) structure, there has been a known method by which a strained Si layer is formed on a SiGe layer formed on a buried oxide (BOX) layer on a Si substrate. In such a structure, the short channel effect (SCE) of the MOSFET is restrained, and a sophisticated semiconductor device is realized.
To realize even more sophisticated semiconductor devices along with further miniaturization, a more advanced strain control technique is essential.
In the “hp45-generation” and later however, semiconductor devices that become smaller in size along with the improvement in device performance and have a high probability that the above described strained semiconductor device is used therein, the gate length Lg in the carrier moving direction in the channel is considered to be 50 nm or smaller. In such a case, the size of the so-called active layer to form the source/drain regions and the gate region in the formation of a device becomes even smaller along with an increase in integration degree. This active layer is formed by cutting out a mesa from the above described globally-strained substrate. Therefore, the strain in the active layer might be relaxed, depending on the pattern size, shape, thickness, substrate dependence, or the like, and systematic consideration should be required.
Strain relaxation occurs mainly due to formation of a free edge at the strained layer that causes strain relaxation. It has become apparent that, in a strained layer that is smaller than several hundreds of nanometers, over which relaxation from the free end can reach, the relaxation becomes significant. Therefore, as described above, to form a strained device on the order of submicron meters in the next- and later-generation devices, it is inevitable to use a control technique for restraining strain relaxation. To effectively use a strained channel in a latest MOSFET, it is critical how to control the strain in the active layer. In view of this, a semiconductor device having strain control layers formed in a strained semiconductor layer beforehand has been suggested to restrain strain relaxation.
Meanwhile, device miniaturization is showing no sign of slowing down, and further miniaturization is being pursued. The source/drain regions at both ends of the gate structure are becoming smaller and smaller along with the miniaturization. Therefore, it is inevitable that the above mentioned strain control layers also become smaller and smaller. To maintain the strain in the channel while coping with the reduction in device size, an increase in the thickness of each strain control layer is realistic.
However, if control layers having excess thicknesses are formed, a high resistance is generated in the source/drain, and the high resistance would not only cancel the improvement in device characteristics made by the strain application but cause many negative factors such as variations among device operations. Therefore, there is a need to take some measures against those negative factors.